A digital system may have two or more clock domains in order to allow circuitry within each clock domain to be more easily optimized to perform the function of that domain. For example, a processor clock domain may operate at a high clock rate in order to perform a greater number of computations per given time period. A peripheral device clock domain may operate at a much lower clock rate in order to simplify design requirements and to reduce cost since peripheral devices generally can tolerate a slower control response time. However, in order for the processor domain to exert control over the peripheral device domain, control signals from the processor domain must be synchronized to the clock signal used in the peripheral device domain.
A commonly used solution for transferring interrupts from the peripheral device domain to the processor domain is to provide a register in the peripheral domain to receive interrupt signals and set a corresponding bit each time an interrupt is received. When the processor reads the interrupt register the processor then writes back the just read value through a synchronization process so that the corresponding bits are cleared from the interrupt register. This reduces the likelihood of loosing an interrupt indication when the interrupt occurs during the synchronization time of the processor read and write cycle. However, this scheme requires additional processor time and power to perform the write back operation.